Design for Trust (Synchronous e-learning)

About This Course

We will first give an overview on the hardware security risk and the roots of trust in ICs. Thereafter, we will cover the various Design for Trust issues, techniques and analyses at various levels, spanning from the manufacturing, chip, netlist, design, and layout levels. Particularly, the manufacturing security includes split manufacturing; the chip level security includes watermarking, fingering, and metering; the netlist security includes logic locking and trojan analysis; the design security includes security primitives (e.g. encryption, random number generators, physical unclonable functions, etc.); and the layout level includes camouflaging.