Design Verification
About This Course
To acquire basic knowledge in verification of digital electronics. The course focuses on verifying the functionality of digital circuits via Verilog testbenches, assertions, creation of verification plans, collecting code coverage, and an introduction to the Universal Verification Methodology (UVM).
At the end of the course, learners will be able to:
1. Describe the verification methodology.
2. Define the testbench.
3. Develop the stimulus generation.
4. Determine the Correctness.
5. Perform assertion-based verification and coverage, gate-level verification, and establish the verification plan.
What You'll Learn
With a focus on topics in verification of digital electronics, the course equips learners with basic skill sets in verifying the functionality of digital circuits via Verilog testbenches, assertions, creation of verification plans, and collection of code coverage. The Universal Verification Methodology (UVM) will also be introduced.
This course comprises 20 hours of lectures and 9 hours of enriching hands-on laboratory sessions ensure mastery at both conceptual and practical application levels. This transformative experience moulds you into a proactive and adaptive thinker, primed for the challenges and innovation-driven demands of advanced manufacturing.
Entry Requirements
This course is suitable for individuals who wish to join or progress within the Engineering Services in the manufacturing/digital electronics industry. Prior knowledge of basic electronics and circuit theories and at least one programming language will be advantageous.